Computer Architecture (3ΚΠ04)
Instructor : Athanasios Kakarountas
Course typeCompulsory
Semester3
TermFall Semester
ECTS5
Teaching hours3
Laboratory hours1
Description
Computer system structure and its subunits operations. Data representation and Instruction Set Architecture (ISA). Benchmarking and performance evaluation. Organization and structure of the Central Processing Unit (CPU). Instruction execution cycle. Computer Arithmetic and Logic Unit (ALU).registers, register file, memory address. Control Unit, microprogramming. Pipeline. Memory hierarchy, organization, types of memory. SRAM, DRAM, cache memory. I/O subunits, polling technique, interrupts, buses, bus arbitrator, Direct Memory Access.
Course objectives
  • Describe the basic structure and organization of a computer
  • Discriminate and describe the various types of computers
  • Identify and describe the fundamental components of a computer
  • Describe in detail the execution cycle of a computer instruction
  • Have knowledge of the memory hierarchy
  • Have knowledge of the differences on cache memory organization
  • Apply software techniques for enhancing execution time of assembly code in a given computer architecture
  • Develop software in a computer resource-aware approach
Textbooks/Bibliography
  • D. Nikolos, “Computer Architecture ”, 2nd ed., Dimitrios Nikolos Publication, 2012, Eudoxus: 22713808.
  • D.A. Patterson, J.L. Hennessy, “Computer Organization and Design: The Hardware and Software Interface”, 4th ed., Kleidarithmos Publications, 2010, Eudoxus: 12561945.
  • W. Stallings, “Computer Organization and Architecture”, 8th ed., Tziola Publications, 2011, Eudoxus: 18548668.
  • C. Hammacher, Z. Vranesic, S. Zaky, “Computer Organization and Architecture”, 1st ed., Publications Epikentro, 2007, Eudoxus: 15120.
Assessment method
Final theory exam 75% Laboratory grade 25%
Course material
http://eclass.uth.gr/eclass/courses/DIB115/